Trace anywhere interconnect

ABSTRACT

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

RELATED APPLICATION

The present application is a divisional application of U.S. Ser. No. 15/189,435 filed on Jun. 22, 2016 by R&D Circuits, Inc. and claims priority thereunder pursuant to 35 USC 120. A provisional application was filed Ser. No. 62/212,894 on Sep. 1, 2015 by R&D Circuits, Inc.

BACKGROUND 1. Field

The present application relates to a method and a structure for creating interconnects that are not bound by the limitations of conventional interconnect technology. In particular the present invention relates to forming an electrical interconnect mechanism between two or more discrete contact points such as but not limited to circuit pads within two or more parallel circuit planes with circuitry formed in three-dimensional space between the aforementioned two or more circuit planes in order to allow for electrical coupling of two or more electrical devises through said interconnect device.

2. The Related Art

Conventional interconnect technology limits the routing of circuitry to the x-y plane by way of conductive traces. These traces are then connected in the z-axis through holes (vias) formed perpendicular to the traces, aligned over the traces. These vias are then coated or plated with a metallization either partially or completely filled, connecting the traces to circuitry formed in the x-y planes above and below.

It is normal for these interconnect structures to have an array of contact pads on either side of the outer major surfaces of the structure and occasionally even on the minor sides or surfaces of the structure. These contact pads are meant to be electrically coupled with electronic components on the outer surfaces. When there are a large number of contact pads or points on each side to be electrically coupled the internal circuitry layers become very dense and require a large number of routing layers. Each of these layers are traditionally formed in layer pairs of two, sandwiched on both sides of a dielectric sheet. These sheets are manufactures concurrently then bonded together with additional dielectric sheet layers forming multilayered structures. Vias are then formed and metalized through or partially through these layer stacks making the required z axis interconnects. Partial or buried vias can be formed and metalized on each of the layer pairs prior to bonding the layers together.

Alternatively, to improve routing density dielectric layers and circuitry layers can be built up one on top of another sequentially with blind vias formed only where necessary. This eliminates the need of through vias, which take up routing space in the x-y planes on layers where the vias is not essential. This via anywhere approach greatly improved routing density but suffers from the cost of time and labor to build these layers sequentially.

SUMMARY

The present invention provides a method and a structure in which an electrical interconnect mechanism is formed having complex connections between two or more discrete contact points such as but not limited to circuit pads within two or more parallel circuit planes with circuitry formed in three-dimensional space between the aforementioned two or more circuit planes, In this way the present invention provides for electrical coupling of two or more electrical devices through said interconnect device. In particular the present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. These wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side. Optionally, forming a second coating of dielectric on the metalized surfaces of the discrete wires to a specific thickness as to approximate a coaxial wire. These formed and metalized dielectric wire may be electrically coupled through the metallization process to discrete metallic circuits on the two or more planes or the discrete parallel circuits may be formed as an integral part of the formed dielectric wires and then metalized along with the dielectric wires. Other embodiments and variations of the present invention are described below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a perspective view of a first embodiment of the present invention;

FIG. 1b is a sectional view of FIG. 1A with component or electrical devices added;

FIGS. 2a-2c are sectional views of three additional embodiments of the present invention of FIG. 1a having metalized outer layers for the dielectric wires and contact points;

FIGS. 3a-3d show alternative embodiments for the dielectric wires of FIG. 1A;

FIG. 4 is another embodiment for the present invention;

FIGS. 5a and b show alternative embodiments for the present invention;

FIGS. 6a-6c shows three additional embodiments of the present invention;

FIG. 7a shows another embodiment of the present invention in which the present invention has a rigid body formed between two or more circuit planes and is filled with a dielectric wherein the fill material extends to the top of the circuit elements;

FIG. 7b shows another embodiment of the present invention in which the present invention has a rigid body formed between two or more circuit planes and is filled with a dielectric wherein the fill material extends to the bottom of the circuit elements;

FIG. 8 is another embodiment of the present invention in which one of the circuit planes of the interconnect of the present invention acts as a plane for the next sequentially build-up plane connected by the formed wires;

FIG. 9 is another embodiment of the present invention showing anon-coplanar interconnect;

FIG. 10 is another embodiment for the present invention in which epoxy scaffolding maintains alignment in the X axis and Y axis and z axis locations of each circuit element;

FIG. 11a is another embodiment of the present invention in which the interconnect is provided with a scaffolding of dielectric, dielectric posts or a dielectric block with penetrations for passage of the wires there through;

FIG. 11b is another embodiment of the present invention in which the interconnect is provided with a scaffolding of dielectric, dielectric posts or a dielectric block with penetrations for passage of the wires there through and showing the interconnect structure when filled with an elastomeric material the scaffolding of dielectric, dielectric posts or a dielectric block with penetrations for passage of the wires there through providing a fixed compression stop of the interconnect structure;

FIGS. 12a, 12b and 12c show alternative embodiments of the present invention in which:

FIG. 12a shows the lattice work of non-conductive dielectric scaffolding for the present invention with the circuit element proud;

FIG. 12b shows the lattice work of non-conductive dielectric scaffolding for the present invention with an air dielectric;

FIG. 12c shows the lattice work of non-conductive dielectric scaffolding for the present invention with the circuit element flush;

FIG. 13 shows another embodiment of the present invention for affixing and electrically coupling two or more terminal points of a electronic component 23 such as but not limited to resistor, capacitors or inductor to the formed wires and the corresponding circuit elements 10 of the corresponding planes 7 wherein each point to be coupled to its corresponding designated power, ground, or signal wires 6 and or circuit elements 10 in the interconnect structure;

FIG. 14 is another embodiment of the present invention in which the wires 6 are extended beyond the rigid body of the interconnect 1 with spring shapes conducive for flexing such as but not limited to coils, cantilever, S-shapes with end points conducive for contacting various shapes of electrical devices such as but not limited to sharp points, crown tips, cup shapes acting as a compliant interconnect coupling two non-coplanar electrical devices.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings of FIGS. 1a -14, FIG. 1a . shows a first embodiment of the present invention in which an electrical interconnect mechanism 5 forms complex connections between two or more discrete contact points 10 (such as but not limited to circuit pads 10 a (FIG. 1b ) or dircrete parallel circuits 8 as shown in FIG. 3a-3d , also signal pads 8 power pads 8 c and ground pads 8 a as shown in FIG. 4 and FIG. 13 are synonymous with discrete circuit elements 8 as well as with circuit pads 10 a as shown in FIG. 1b ) within two or more parallel circuit planes 7 with circuitry 6 formed in three-dimensional space between the aforementioned two or more circuit planes 7 in order to provide for electrical coupling of two or more electrical devices 8 FIG. 1b through the interconnect device 5.

As shown FIG. 1a , three-dimensionally routed dielectric wires 6 are formed between discrete points 10 on the two or more parallel circuit planes 7. These wires 6 may be freely routed in three-dimensional space to create the most efficient routing between the two arbitrarily defined points 10 on the two or more parallel circuit planes 7. The outer surfaces of these three dimensional dielectric wires 6 prior to electrically coupling the discrete wires 6 to their respective discrete contact points 10 should be metalized 3 (see FIG. 2). Optionally, the three dimensional dielectric wires 6 (FIG. 2) may be either solid metal wires 3 b (FIG. 6a ) with an optional coating of dielectric 6 b (FIG. 6b ) as well as an optional coating of metallization on the dielectric 3 c (FIG. 6c ) or may be a metalized dielectric 3 (FIG. 3d ) with a second coating of dielectric 6 a (FIG. 3c ) or may also include a second coating of dielectric 6 a (FIG. 3b ) and a second coating of metallization 3 a (FIG. 3b ). Two or more of these wires 6 (FIG. 2c ) may be placed into intimate contact with one another electrically coupling each other as well as two or more discrete contact pads 10 a (FIG. 2c ). These electrically coupled contact pads 10 a may be on opposite sides (FIG. 2a ) or on the same side (FIG. 2b ) of the structure 5 (FIG. 1a ). Optionally, a second coating of dielectric 6 a may be formed on the metalized surfaces of the discrete wires 6 to a specific thickness so as to approximate a coaxial wire (SEE FIGS. 3a-3b ). These formed and metalized dielectric wires may be electrically coupled through the metallization process to discrete metallic circuits on the two or more planes 7 as in (FIG. 3c ) or the discrete parallel circuits 8 (FIG. 3d ) may be formed as an integral part of the formed dielectric wires 6 and then metalized along with the dielectric wires 6 (see FIG. 3d ).

In the embodiment for the optionally formed second coating of dielectric 6 a and metallization 3 a of the wires 6 the second metallization 3 a on the coated wire 6 is limited to just short of making contact to the discrete circuit elements on either plane 7 (FIG. 3a ). This metallization should be recessed from the discrete circuit elements in the range of 1 um to 50 um (See FIG. 3a embodiment of the present invention).

In another embodiment of the present invention the second metalization coating and or the second dielectric layer on the formed dielectric wires is in intimate contact with one another coupling the outer metallization electrically to each other as well as to one or more points on the outer surface circuit planes. This will have the effect of providing ground shielding and or coaxial wires (See FIG. 4).

In lieu of ground shielding formed around the discrete circuit wires 6, alternatively a dielectric wall 15 or plane 15 may be formed in the z-axis or vertically in the structure, transposed between the outer surface circuit planes 7, metalized with the end points electrically coupled to the discrete circuits patterns 8,8 a (FIG. 5a ) on one or both planes. Tying these vertical planes to ground 8 a will provide for shielding of adjacently routed circuit wires as well as the ability to control the impedance of these wires as shown in FIGS. 5 a and 5 b.

FIGS. 7a and 7b shows two embodiments in which a rigid body 16 is formed between these two or more circuit planes 7 by filling the area between the planes with a dielectric 14, such as but not limited to epoxy. This fill material 14 may extend to the bottom of the circuit elements (see FIG. 7b ) making the elements superior to the filled dielectric or to the top of the circuit elements (see FIG. 7a ) making the elements flush to the fill material. Repeating one or more of the previously described processes of the previously described embodiments with one of the circuit planes 7 of the previously formed interconnect 1 acting as one of the planes for the next sequentially formed build-up circuit plane 7 connected by these formed wires 6 (See the embodiment of FIG. 8).

FIG. 9 shows another embodiment of the present invention in which instead of filling the aforementioned interconnect mechanism 1 with rigid material such as epoxy 14, the interconnect structure 1 is filled with a compliant material such as an elastomer 19 to maintain alignment of the three dimensional wires 6 and circuitry end points to their desired location as well as allowing for z-axis compliance in order to allow for electrical coupling of two non-coplanar surfaces 7 a intended to be coupled by said electrical interconnect mechanism 1.

FIG. 10 shows another embodiment of the present invention in which instead of filling the entire internal area of the interconnect mechanism with an epoxy, forming a scaffolding 17 a with the least amount on material, such as an epoxy, in intimate contact with each of the circuit element on each of the planes transposed between both circuit planes maintaining the z-axis spacing between each plane as well as the x-y location of each of the circuit elements. This scaffolding structure will provide the interconnect 1 with a rigid structure while maintaining air around the formed circuits wires.

FIG. 11a shows another embodiment of the present invention in which around said interconnect a scaffolding of dielectric, dielectric posts or a solid dielectric block 17 a. FIG. 11b shows a similar embodiment of the present invention but with said scaffolding of dielectric, dielectric posts or a solid dielectric block with penetrations 21 provided to permit entry of the wires 6. When used in conjunction with a filled elastomeric material, said dielectric structure provides a fixed compression stop of the interconnect structure 1 to prevent damage to the wires 6 due to over compression (FIG. 11b ).

Designing the free flow of the three dimensionally formed aforementioned wires to have shapes such as but not limited to coils, cantilevers and S-shapes to provide spring like characteristics to allow for the compliance of the wires while resisting stress cracking in the metal and or dielectric (See FIG. 1a ).

FIG. 12a shows another embodiment of the present invention in which a lattice work of non-conductive dielectric scaffolding 17 b transposed between the two circuit planes 7 in intimate contact to the circuit elements within the circuit planes 7 is provided which both provides for alignment of the individual contact points or circuit elements 10 within the circuit planes 7 and either providing rigidity for the entire structure 1 or allowing for some compliance of the entire structure in the z-axis, while optionally also allowing for air dielectric 22 around the aforementioned wires (See FIG. 12b ). FIG. 12a shows the embodiment with the circuit elements superior to the dielectric and FIG. 12c shows the embodiment with the circuit elements flush. The scaffolding can be of varying structures known in the art of mechanical engineering to provide the desired properties described above.

FIG. 13 shows affixing and electrically coupling two or more terminal points 24 of a electronic component 23 such as but not limited to a resistor, capacitors or inductor to the formed wires and the corresponding circuit elements of the corresponding planes 7. Each point to be coupled to its corresponding designated power, ground, or signal wires 6 and or circuit elements 10 in the interconnect structure 1. In this way capacitance, resistance, inductance, or any other electronic function is provided to the points of the electrical devices the interconnect 1 is intended to couple. (See FIG. 13)

FIG. 14 shows another embodiment of the present invention in which the wires 6 are extended beyond the rigid body of the interconnect 1 with shape such as but not limited to coils, cantalievers, and S-shapes to provide spring like characteristics to allow for the compliance of the wires while resisting stress cracking in the metal and or dielectric and end points conducive for contacting various shapes of electrical devices such as but not limited to sharp points, crown tips or cup shapes 25 acting as a compliant interconnect coupling two non-coplanar electrical devices. Providing the ability for pitch translation and pin remapping as well as compliant probing in one integrated structure. Further, each of the aforementioned embodiments of the present invention can be built with one or more silicon wafer ICs' creating multi chip modules interconnecting the two or more ICs' where a silicon layer is the base circuit plane.

Further, each of the aforementioned embodiments of the present invention can be built with one or more silicon wafer ICs' creating redistribution packaging for the IC.

Further, each of the aforementioned embodiments of the present invention can be built on a flexible circuit base.

The method for the above described embodiment structure is as follows: In the case of a trace anywhere interconnect with dielectric core wires for the present invention, the starting point is with a flat carrier of glass, ceramic or some other smooth, flat material such as but not limited to s smooth metallic block. Next one should temporarily bond a sheet of metallic foil preferably Cu to the flat material carrier to keep the Cu flat with a suitable bonding material such as but not limited to adhesive or wax. This foil thickness should be in the range but not limited to 10 um to 35 um. Next, on top of the Cu foils, utilizing commercially available 3D printing techniques know in the art, form dielectric wires attached to the Cu foil grow-up from predetermined locations on the foil to predetermined location in free space in the z axis. The foil may be treated to promote adhesion of the dielectric wires through micro-etching plasma or other surface treatment known in the art. These wires will typically be in the range of 1 um to 50 um in diameter. These wires will be built up to a z-axis height approximately 25 um to 100 um above the overall height of the planned interconnect mechanism typically from 100 um to 0.200″ thick.

Next, the free formed wires extending from the Cu sheet are metalized with electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art. The thickness of this metallization will typically be in the range of 1 um to 25 um. This metallization will in effect coat the dielectric wires as well as the exposed surface area of the base foil making the base foil and the coated wires electrically coupled.

Optionally, the metalized dielectric wires can be coated again with a dielectric via a dip operation, silicon Chemical Vapor deposition (SCVD) Silica Pulsed layer Deposition (PLD), Titania Atomic Layer Deposition (ALD) or other techniques known in the art. During this process the top side, of the base foil metallization can be coated as well, electrically isolating it from further processes.

The coated wires are then (optionally) metalized via the techniques previously described. This metallization will have the effect of shorting all the surfaces of the formed wires together. Tying this metallization to one or more ground wires or outer circuit layers in effect creates ground shielding for all wires as well as approximates coaxial wires for all signal wires. Coupling this ground metallization can be achieved through selective removal of the outer coating of dielectric, via laser ablation, Milling or some other technique known in the art, from the wires or areas of the base copper designed to be ground when the interconnect ultimately couples two or more electronic devices. Now that the wires are formed with or without a second dielectric and second metallization the structure can be filled with a dielectric such as but not limited to epoxy via a molding operation (commonly known in the art) curing the epoxy into a rigid substrate. It would be best to over mold the epoxy beyond the top end points of the formed wires by approximately 25 um-100 um. This permits enough material for a planarization process via grinding, sanding, lapping or other techniques know in the art. In the embodiment of the wires having a second dielectric and second metallization the top tips of the wires may be coated with a temporary coating such as wax or a temporary polymer to prevent metallization from forming at the last 25 um to 100 um (typically) on the second dielectric layer.

Planarization also reveals the tops of the metalized wires providing the opportunity to build up a second circuit layer while electrically coupling said circuit layer to the wires and the base foil. If the tips of the coated wires have been spared from secondary metallization then carefully controlling the planarization of the interconnect substrate in the z-axis will reveal the first metalized layer of the formed wire exposing it to be electrically coupled to the aforementioned second circuit plane formation without coupling the aforementioned optional second metallization of the formed wire to the second circuit plane layer.

The aforementioned second circuit plane layer can then be formed via electro-less plating, Chemical vapor deposition, sputter coating, electro-plating, or any other technique known in the art. This conductive metallization is preferably Cu, Au or any other suitable conductive material and or multiple layers of different materials. After lifting the interconnect off the smooth substrate. The primary bottom metallic layer, and the secondary top layer may now be formed into discreet circuitry through a traditional photo lithographic etching processes known in the art. The contact points or pads formed through this circuitization process can be additionally plated with suitable metallic alloys for the desired application such as but not limited to wear resistance or solder-ability.

Alternatively, in lieu of a dielectric core in the aforementioned wires a metal core may be substituted through the use of negative 3D printing techniques utilizing but not limited to negative working photo sensitive epoxy known in the art whereby a temporary dielectric is formed through the entire active area of the interconnect except where the core wire metallization is to be formed. Then the metallization is formed through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or other techniques known in the art to form a sold metallic wire structure. Alternatively, varying metals of varying thicknesses can be formed on the inner walls of the voided structures in the epoxy layers providing the desirable electrical and mechanical properties for the end application. Then the temporary epoxy is removed through stripping techniques known in the art and freestanding metallic wires or tubes remain for continued processing described above.

Alternatively, dielectric cored, metallic cored or metallic tubes with or without additional layers of dielectric and metallization for shielding or coaxial vias could be formed on to discrete metallic pads or circuits pre-formed on to said smooth glass or smooth ceramic or other suitable material through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art. Having their dimensions defined through a temporary photo-lithographic process common in the art. Further, these pads or circuits could be formed utilizing a laser stenciling process whereby a metallic foil is adhered temporarily to the smooth flat base material with an adhesive or wax and the aforementioned techniques for wire formation may be built on top of the discrete pads or circuitry.

Further when the end points of the formed wires are formed discrete pads and or circuitry with varying geometric shapes may be formed based on the intended application of the inter-connect. Solder-able pads or pins of varying shapes for making contact to electrical terminals may be formed and metalized as described previously. This formation and metallization of the end points of the formed wires in one step saves additional processing time and in combination with the formation of the discrete pads on the base metal layer provides the opportunity for flush circuit pads on both ends on the inter-connect once the aforementioned epoxy molding process in completed.

Alternatively, in any of the embodiments described above an elastomer or rubber compound potting material may be substituted for a rigid potting compound providing the interconnect terminals with compliance for mating non-coplanar electronic device surfaces. By varying the durometer of the potting material as well as the formed wires material, thickness, length and shape we may control the total amount of compliance, force and longevity of each of the formed wire mating terminals.

Alternatively, in the event of an aforementioned compliant interconnect a latticework, posts, or a solid block of a suitable hard material such as but not limited to epoxy may be formed within the open spaces of the inter-connect not occupied by the formed wires or the compliant potting material. These structures can be formed through the same 3D printing techniques, in the open spaces of the interconnect body, with a height slightly thinner than the overall thickness of the interconnect (˜10 um to 200 um) providing the interconnect structure with a hard compression stop against the two mating surfaces of the devices intended to be electrically coupled. This will prevent over compression and damage of the interconnect structure.

While presently preferred embodiments have been described for purposes of the disclosure, numerous changes in the

arrangement of method steps and those skilled in the art can make apparatus parts. Such changes are encompassed within the spirit of the invention as defined by the appended claims. 

What is claimed:
 1. A method for fabricating an interconnect mechanism or device comprising the steps of: providing a flat carrier of glass, ceramic or some other smooth, flat material such as but not limited to s smooth metallic block; temporarily bonding a sheet of metallic foil preferably Cu to the flat material carrier to keep the Cu flat with a suitable bonding material such as but not limited to adhesive or wax. Said sheet of foil having a foil thickness in a range but not limited to 10 um to 35 um; forming on top of the Cu foils dielectric wires attached to the Cu foil grow-up from predetermined locations on the foil to predetermined location in free space in the z axis by utilizing commercially known 3d printing techniques; treating said foil to promote adhesion of the dielectric wires through micro-etching plasma or other surface treatment; said wires are in a range of 1 um to 50 um in diameter and are built up to a z-axis height approximately 25 um to 100 um above an overall height of the planned interconnect mechanism in a range of from 100 um to 0.200 thick; metalizing the free formed wires extending from the Cu sheet with one of either electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art, said thickness of this metallization will typically be in the range of 1 um to 20 um; said metallization coating the dielectric wires as well as the exposed surface area of the base foil making the base foil and the coated wires electrically coupled.
 2. The method for fabricating an interconnect mechanism or device according to claim 1 wherein the metalized dielectric wires are be coated again with a dielectric.
 3. The method according to claim 2 wherein said coating with said dielectric is done via a dip operation, silicon Chemical Vapor deposition (SCVD) Silica Pulsed layer Deposition (PLD), Titania Atomic Layer Deposition (ALD) or other techniques known in the art.
 4. The method according to claim 2 wherein during this process a top side, of the base foil metallization can be coated as well, electrically isolating it from further processes.
 5. The method according to claim 2 wherein the coated wires are then metallized to short all the surfaces of the formed wires together.
 6. The method according to claim 5 wherein tying this metallization to one or more ground wires or outer circuit layers t creates ground shielding for all wires as well as approximates coaxial wires for all signal wires.
 7. The method according to claim 6 wherein coupling this ground metallization can be achieved through selective removal of the outer coating of dielectric, via laser ablation, or some other technique known in the art, from the wires or areas of the base copper designed to be ground when the interconnect ultimately couples two or more electronic devices.
 8. The method according to claim 1 wherein the wires are then formed with or without a second dielectric and second metallization and the structure can be filled with a dielectric such as but not limited to epoxy via a molding operation) curing the epoxy into a rigid substrate. It would be best to over mold the epoxy beyond the top end points of the formed wires by approximately 25 um-100 um. thereby permitting enough material for a planarization process via grinding, sanding, lapping or other techniques know in the art.
 9. The method according to claim 7 wherein the wires having a second dielectric and second metallization top tips of the wires may be coated with a temporary coating such as wax or a temporary polymer to prevent metallization from forming at the last 25 um to 100 um on a second dielectric layer.
 10. The method according to claim 8 wherein planarization also reveals the tops of the metalized wires providing the opportto build up a second circuit layer while electrically coupling said circuit layer to the wires and the base foil so that if tips of the coated wires have been spared from secondary metallization then carefully controlling the planarization of the interconnect substrate in the z-axis will reveal the first metalized layer of the formed wire exposing it to be electrically coupled to the aforementioned second circuit plane formation without coupling the aforementioned optional second metallization of the formed wire to the second circuit plane layer.
 11. The method according to claim 10 wherein said second circuit plane layer is then formed via electro-less plating, Chemical vapor deposition, sputter coating, electro-plating, or any other technique known in the art.
 12. The method according to claim 1 wherein the conductive metallization is preferable Cu, Au or any other suitable conductive material and or multiple layers of different materials.
 13. The method according to claim 10 wherein after lifting the inter-connect off the smooth substrate, a primary bottom metallic layer, and a secondary top layer is formed into discreet circuitry through a traditional photo lithographic etching processes.
 14. The method according to claim 13 wherein said contact points or pads are formed through this circuitization process are additionally plated with suitable metallic alloys for the desired application such as but not limited to wear resistance or solder-ability.
 15. The method according to claim 1 wherein instead of a dielectric core in the wires, a metal core is substituted through use of negative 3D printing techniques utilizing but not limited to negative working photo sensitive epoxy whereby a temporary dielectric is formed through the entire active area of the interconnect except where the core wire metallization is to be formed. Then metallization is formed through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or other techniques known in the art to form a sold metallic wire structure.
 16. The method according to claim 15 wherein varying metals of varying thicknesses are formed on inner walls of voided structures in epoxy layers providing the desirable electrical and mechanical properties for the interconnect mechanism, then temporary epoxy is removed through stripping techniques and freestanding metallic wires or tubes remain for continued processing.
 17. The method according to claim 15 wherein dielectric cored, metallic cored or metallic tubes with or without additional layers of dielectric and metallization for shielding or coaxial vias could be formed on to discrete metallic pads or circuits pre-formed on to said smooth glass or smooth ceramic or other suitable material through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art
 18. The method according to claim 17 wherein dimensions of said discrete metallic pads are defined through a temporary photo-lithographic process common in the art and the pads or the circuits are formed utilizing a laser stenciling process whereby a metallic foil is adhered temporarily to the smooth flat base material with an adhesive or wax for wire formation may be built on top of the discrete pads or circuitry.
 19. The method according to claim 15 wherein the end points of the formed wires are discrete pads and or circuitry with varying geometric shapes formed based on an intended application of the inter-connect and solderable pads or pins of varying shapes for making contact to electrical terminals are formed and metalized
 20. The method according to claim 19 wherein the formation and metallization of the end points of the formed wires in one step saves additional processing time and in combination with the formation of the discrete pads on the base metal layer and provides the opportunity for flush circuit pads on both ends on the inter-connect once the epoxy molding process in completed.
 21. The method according to claim 1 wherein an elastomer or rubber compound potting material is substituted for a rigid potting compound providing the interconnect terminals with compliance for mating non-coplanar electronic device surfaces and by varying the durometer of the potting material as well as the formed wires material, thickness, length and shape the total amount of compliance, force and longevity of each of the formed wire mating terminals is controlled.
 22. The method according to claim 1 wherein, in the event of a compliant interconnect a latticework, posts, or a solid block of a suitable hard material such as but not limited to epoxy is formed within the open spaces of the inter-connect not occupied by the formed wires or the compliant potting material.
 23. The method according to claim 22 wherein said structures are formed through 3D printing techniques, in open spaces of the interconnect body, with a height slightly thinner than the overall thickness of the interconnect in a range of ˜10 um to 200 um providing the interconnect structure with a hard compression stop against the two mating surfaces of the devices intended to be electrically coupled thereby preventing over compression and damage of the interconnect structure. 